FPL' 22

FPL' 22

32nd International Conference on Field Programmable Logic and Applications hosted by Queens University Belfast, United Kingdom.

AMD HACC Workshop: Introduction to the Heterogeneous Accelerated Compute Clusters

Venue: 2.022, Ashby Building, QUB.

Organizer: Cathal McCabe (AMD), Michaela Blott (AMD), Mario Ruiz (Xilinx), Gustavo Alonso (ETH Zurich), Javier Moya Paya (ETH Zurich), Ken O’Brien (AMD)

Abstract: The HACC program (formerly known as the XACC program) is expanding to encompass additional adaptive computing resources. Each HACC will be enabled with high-end servers with multiple GPU (AMD Instinct), FPGA (Alveo U55C) and ACAP (VCK5000) accelerator cards. The Xilinx VCK5000 Versal development card is built on the Xilinx 7nm Versal® ACAP architecture and is designed for adaptable intelligent (AI) engine development with Vitis. These new nodes are in addition to existing compute nodes enabled with Alveo Accelerator cards. The HACCs are provided free-of-charge by AMD and consist of leading-edge Adaptive Compute hardware. FPL attendees are eligible to join the HACC program and get access to the HACC resources for their own research. This workshop is also intended to bring like-minded researchers together and offer networking opportunities and stimulate collaboration discussions with existing HACC users and new users.

Agenda

  • Session 1:
    • Introduction to the AMD Heterogeneous Accelerated Compute Clusters (HAACs); Cathal McCabe, Michaela Blott (AMD Adaptive and Embedded Computing Group)
    • ETH Zurich HACC overview & research Prof Gustavo Alonso (ETH Zurich)
    • Paderborn HACC Overview and Research Prof Christian Plessl (University of Paderborn)
  • Break
  • Session 2:
    • HACC Tutorial & demo, Javier Moya Paya (ETH Zurich), Mario Ruiz (AMD Adaptive and Embedded Computing Group)
    • Research talks
      • ACCL: FPGA Accelerated Collectives Communication Library, Ken O’Brien (AMD Adaptive and Embedded Computing Group)
      • ACCL-driven Multi-FPGA Design for Distributed Processing of Scientific Workloads in Shallow Water Simulations, Marius Meyer (University of Paderborn)
      • Sketch Data Analytics on FPGA, Monica Chiosa (ETH Zurich)
  • Q&A/Discussion
  • Closing