The 32nd edition of FPL will be a hyrbid event. The main conference will take place from 29 August until 31 August, 2022. The workshops and tutorials will be organized on 1 September until 2 Septemer, 2022.

Main Conference

Main conference will be held at the Queens Film Theatre, Belfast UK from the 29th of August to 31st of August.

Time\Day Monday 29th Tuesday 30th Wednesday 31st
08:30 - 08:45 Welcome    
08:45 - 10:15 Accelerators I FPGA Design Virtualization & Emulation
10:15 - 10:40 Coffee & Posters Coffee & Posters Coffee & Posters
10:40 - 11:40 Accelerators II Convolutional Neural Nets I Convolutional Neural Nets II
11:40 - 12:40 Keynote I
Nele Mentens
Keynote II
Phil James-Roxby
Keynote III
Torsten Hoefler
12:40 - 13:40 Lunch & Posters Lunch & Posters Lunch & Posters
13:40 - 14:40 Reconfigurable Computing Scalable Systems Keynote IV
Finbarr O’Regan
14:40 - 15:00 Coffee & Posters Coffee & Posters Coffee & Posters
15:00 - 15:30 Posters Panel Posters Panel Posters Panel
15:30 - 17:00 Accelerators III High Level Synthesis
Banquet (17:00)
Tunable Circuits
PhD Forum and Demo (16:10)

Tutorials and Workshops

Tutorials and Workshops will be held at the Ashby Building, QUB on the 1st and 2nd September, 2022. Detailed program for each day can be seen here

Monday 29th

Accelerators I

08:45 - 10:15 Theatre 1
  Accurate, Low-latency, Efficient SAR Automatic Target Recognition on FPGA, Bingyi Zhang, Rajgopal Kannan, Viktor Prasanna and Carl Busart
  BunchBloomer: Cost-Effective Bloom Filter Accelerator for Genomics Applications, Seongyoung Kang, Tarun Sai Ganesh Nerella, Shashank Uppoor and Sang-Woo Jun
  TRAC: Compilation-based Design of Transformer Accelerators for FPGAs, Patrick Plagwitz, Frank Hannig and Jürgen Teich
  GraphScale: Scalable Bandwidth-Efficient Graph Processing on FPGAs, Jonas Dann, Daniel Ritter and Holger Fröning

Accelerators II

10:40 - 11:40 Theatre 1
  Ultra-Flow: An Ultra-fast and High-quality Optical Flow Accelerator with Deep Feature Matching on FPGA, Yehua Ling, Yuanxing Yan, Kai Huang and Gang Chen
  Resource Optimal Squarers for FPGAs, Andreas Boettcher, Martin Kumm and Florent de Dinechin
  Synthesized Garbage Collection for FPGA Accelerators, Martha Barker, Martha Kim and Stephen A. Edwards
Reconfigurable Computing
13:40 - 14:40 Theatre 1
  Virtualization of Reconfigurable Mixed-Criticality Systems, Cornelia Wulf, Najdet Charaf and Diana Goehringer
  TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework, Yunhui Qiu, Yuhang Cao, Yuan Dai, Wenbo Yin and Lingli Wang
  HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation, Yuanlong Xiao, Aditya Hota, Dongjoon Park and Andre DeHon

Poster Panel I

15:00 - 15:30 Theatre 1 (Posters displayed at Brian Friel Theatre)
  Auto-ViT-Acc: FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization, Zhengang Li, Mengshu Sun, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin and Zhenman Fang
  Reduction of Bitstream Size for Low-Cost iCE40 FPGAs, Clemens Fritzsch, Joern Hoffmann and Martin Bogdan
  A-U3D: A Unified 2D/3D CNN Accelerator on the Versal Platform for Disparity Estimation, Tianyu Zhang, Dong Li, Hong Wang, Yunzhi Li, Xiang Ma, Wei Luo, Yu Wang, Yang Huang, Yi Li, Yu Zhang, Xinlin Yang, Xijie Jia, Qiang Lin, Lu Tian, Fan Jiang, Dongliang Xie, Hong Luo and Yi Shan
  FPGA Roofline modeling and its Application to Visual SLAM, Ioanna-Maria Panagou, Maria Rafaela Gkeka, Alexandros Patras, Spyros Lalis, Christos D. Antonopoulos and Nikolaos Bellas
  The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic Gates, Fan Liu, Xiaole Cui and Sunrui Zhang
  Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches, Kohei Ito, Ryota Yasudo and Hideharu Amano
  Reducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory Patterns, Robert Szafarczyk, Syed Waqar Nabi and Wim Vanderbauwhede
  Model-based Generation of Hardware/Software Architectures for Robotics Systems, Ariel Podlubne, Johannes Mey, Sergio Pertuz, Uwe Aßmann and Diana Goehringer
  DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks, Jan Sommer, M. Akif Özkan, Oliver Keszocze and Jürgen Teich

Accelerators III

15:30 - 17:00 Theatre 1
  TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations, Chan-Wei Hu, Jiang Hu and Sunil Khatri
  A Flexible Real-Time Stereo Vision Architecture for Multiple Data Streams with Runtime Configurable Parameters, Zhaoteng Meng, Lin Shu and Jie Hao
  Real-Time Waveform Matching with a Digitizer at 10 GS/s, Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich and Stefan Wildermann
  Optimized Mappings for Symmetric Range-Limited Molecular Force Calculations on FPGAs, Chunshu Wu, Sahan Bandara, Tong Geng, Anqi Guo, Pouya Haghi, Woody Sherman, Vipin Sachdeva and Martin Herbordt

Tuesday 30th

FPGA Design

08:45 - 10:15 Theatre 1
  Auto-Tuning of Raw Filters for FPGAs, Tobias Hahn, Stefan Wildermann and Jürgen Teich
  Accelerating Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform, Yuan Meng, Kannan Rajgopal and Viktor Prasanna
  DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators, Babar Khan, Carsten Heinz and Andreas Koch
  Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats, Sahand Kashani, Mahyar Emami and James Larus

Convolutional Neural Nets I

10:40 - 11:40 Theatre 1
  H-GCN: A Graph Convolutional Network Accelerator on Versal ACAP Architecture, Chengming Zhang, Tong Geng, Anqi Guo, Jiannan Tian, Martin Herbordt, Ang Li and Dingwen Tao
  XVDPU: A High Performance CNN Accelerator on the Versal Platform Powered by the AI Engine, Xijie Jia, Yu Zhang, Guangdong Liu, Xinlin Yang, Tianyu Zhang, Jia Zheng, Dongdong Xu, Hong Wang, Rongzhang Zheng, Satyaprakash Pareek, Lu Tian, Dongliang Xie, Hong Luo and Yi Shan
  Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units, Mário Véstias, Rui P. Duarte, José T. DeSousa, Horácio Neto

Scalable Systems

13:40 - 14:40 Theatre 1
  FSHMEM: Supporting Partitioned Global Address Space on FPGAs for Large-Scale Hardware Acceleration Infrastructure, Yashael Faith Arthanto, David Ojika and Joo-Young Kim
  Direct Device-to-Device Physical Page Migrations in Multi-FPGA Shared Virtual Memory Systems, Torben Kalkhof and Andreas Koch
  Near-Memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures and Optimizations, Veronia Iskandar, Mohamed A. Abd El Ghany, Diana Goehringer

Poster Panel II

15:00 - 15:30 Theatre 1 (Posters displayed at Brian Friel Theatre)
  A Unifying Architecture for Heterogeneous Processing Elements on FPGA, Stewart Denholm and Wayne Luk
  Maia: Matrix Inversion Acceleration Near Memory, Bahar Asgari, Dheeraj Ramchandani, Amaan Marfatia and Hyesoon Kim
  GRAEBO: FPGA General Routing Architecture Exploration via Bayesian Optimization, Su Zheng, Jiadong Qian, Hao Zhou and Lingli Wang
  Dynamic Heap Management in High-Level Synthesis for Many-Accelerator Architectures, Argyris Kokkinis, Dionysios Diamantopoulos and Kostas Siozios
  A High-Performance FPGA Accelerator for CUR Decomposition, M.A.A Abdelgawad, Ray C.C. Cheung and Hong Yan
  A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems, Ahmed Kamaleldin and Diana Goehringer
  SDMA: An Efficient and Flexible Sparse-Dense Matrix-Multiplication Architecture for GNNs, Yingxue Gao, Lei Gong, Chao Wang, Teng Wang and Xuehai Zhou
  FRA-FPGA: Fast Reconfigurable Automata Processing on FPGAs, Peng Zhang, Shijun Zhang, Shang Li, Jin Zhang, Shaoxun Liu and Youjun Bu
  Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals, Nicolai Fiege, Patrick Sittel and Peter Zipf

High Level Synthesis

15:30 - 17:00 Theatre 1
  POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations, Ruizhe Zhao, Jianyi Cheng, Wayne Luk and George A Constantinides
  Dynamic Inter-Block Scheduling for HLS, Jianyi Cheng, Lana Josipović, George Constantinides and John Wickerson
  Unleashing Parallelism in Elastic Circuits with Faster Token Delivery, Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic and Paolo Ienne
  Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis, Nicolai Fiege, Patrick Sittel and Peter Zipf

Wednesday 31st

Virtualization & Emulation

08:45 - 10:15 Theatre 1
  EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs, Yee Yang Tan, Felix Staudigl, Lukas Jünger, Anna Drewes, Rainer Leupers and Jan Moritz Joseph
  ERMES: Efficient Racetrack Memory Emulation System based on FPGA, Fanny Spagnolo, Salim Ullah, Pasquale Corsonello and Akash Kumar
  Increasing Flexibility of FPGA Virtualization for ARM-based Cloud Applications, Jinjie Ruan, Kan Shi, Yisong Chang, Ke Zhang and Yungang Bao
  A Scalable Many-core Overlay Architecture on an HBM2-Enabled Multi-die FPGA, Riadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku

Convolutional Neural Nets II

10:40 - 11:40 Theatre 1
  Design of High-Throughput Mixed-Precision CNN Accelerators on FPGA, Cecilia Latotzke, Tim Ciesielski and Tobias Gemmeke
  Feature dimensionality in CNN acceleration for high-throughput network intrusion detection, Laurens Le Jeune, Toon Goedemé and Nele Mentens
  Data and Computation Reuse in CNNs using Memristor TCAMs, Rafael Fão de Moura, João Paulo Cardoso De Lima, Luigi Carro

Poster Panel III

15:00 - 15:30 Theatre 1 (Posters displayed at Brian Friel Theatre)
  Assessing the Effectiveness of Active Fences Against SCAs for Multi-Tenant FPGAs, Christos Diktopoulos, Konstantinos Georgopoulos, Andreas Brokalakis, Gergios Christou, Gregory Chrysos, Ioannis Morianos and Sotirios Ioannidis
  Breaking an FPGA-integrated NIST SP 800-193 compliant TRNG Hard-IP core with on-chip voltage-based fault attacks, Dennis Gnad, Jiaqi Hu and Mehdi Tahoori
  Modeling and Exploration of Elastic CGRAs, Omar Ragheb, Tianyi Yu, David Ma and Jason H. Anderson
  Ultra Low Latency Machine Learning for Scientific Edge Applications, Narasinga Miniskar, Aaron Young, Frank Liu, Willem Blokland, Anthony Cabrera and Jeff Vetter
  SAMO: Optimised Mapping of Convolutional Neural Networks to Streaming Architectures, Alexander Montgomerie-Corcoran, Zhewen Yu and Christos Bouganis
  A Lightweight Multi-Attack CAN Intrusion Detection System on hybrid FPGAs, Shashwat Khandelwal and Shreejith Shanker
  A Framework for Neural Network Inference on FPGA-Centric SmartNICs, Anqi Guo, Tong Geng, Yongan Zhang, Pouya Haghi, Chunshu Wu, Cheng Tan, Yingyan Lin, Ang Li and Martin Herbordt
  RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices, Andrew Boutros, Eriko Nurvitadhi and Vaughn Betz
  SkeletonGCN: A Simple Yet Effective Accelerator For GCN Training, Chen Wu, Zhuofu Tao, Kun Wang and Lei He
  Optimizing Graph Neural Networks for Jet Tagging in Particle Physics on FPGAs, Zhiqiang Que, Marcus Loo, Hongxiang Fan, Maurizio Pierini, Alexander Tapper and Wayne Luk

Tunable Circuits

15:30 - 16:10 Theatre 1
  A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits, Carmine Rizzi, Andrea Guerrieri, Paolo Ienne and Lana Josipovic
  Tunable Fine-grained Clock Phase-shifting for FPGAs, Bardia Babaei and Dirk Koch

PhD Forum

16:10 - 17:00 Theatre 1
  Mining CryptoNight-Haven on the Varium C1100 Blockchain Accelerator Card, Lucas Bex, Furkan Turan, Michiel Van Beirendonck and Ingrid Verbauwhede
  Spade: An HDL Inspired by Modern Software Languages, Frans Skarman and Oscar Gustafsson
  High Performance FPGA-based Post Quantum Cryptography Implementations, Ziying Ni, Ayesha Khalid and Maire O’Neill
  A Framework for Intrinsic Evolvable Systems, Najdet Charaf and Diana Goehringer
  Virtualization of Embedded Reconfigurable Systems, Cornelia Wulf and Diana Goehringer
  Acceleration of Post Quantum Digital Signature Scheme CRYSTALS-Dilithium on Reconfigurable Hardware, Donal Campbell
  Precise Characterizing of FPGAs in Production Systems, Bardia Babaei and Dirk Koch

Demo Papers

16:10 - 17:00 Theatre 1
  Logic Shrinkage: A Neural Architecture Search-Based Approach to FPGA Netlist Generation, Marie Auffret, Erwei Wang and James Davis
  FPL Demo: 400G FPGA Packet Capture Based on Network Development Kit, Jakub Cabal, Jiří Sikora, Štěpán Friedl, Martin Špinler and Jan Kořenek
  Hot Reconfiguration - Partial Reconfiguration without Bounds, Myrtle Shah
  FPL Demo: An FPGA-IP Prototype Chip for MEC devices, Morihiro Kuga, Masahiro Iida and Hideharu Amano
  FPL Demo: Kyokko - An Aurora 64b66b compatible 100 Gbps Communication Controller, Akinobu Tomori and Yasunori Osana
  FPL Demo: A Flexible and Scalable Quantum-Classical Interface based on FPGAs, Takefumi Miyoshi, Keisuke Koike, Shinich Morisaka, Hidehisa Shiomi, Kazuhisa Ogawa, Yutaka Tabuchi and Makoto Negoro
  FPL Demo: SERVE: Agile Hardware Development Platform with Cloud IDE and Cloud FPGAs, Zelin Wang, Ke Zhang, Yisong Chang, Yanlong Yin, Yuxiao Chen, Ran Zhao, Songyue Wang, Mingyu Chen and Yungang Bao

Industry Demo

16:10 - 17:00 Theatre 1
  GNU Radio Spectrum Analysis using 100G Data Offload from the RFSoC 4x2, Marius Šiaučiulis, Joshua Goldsmith, David Northcote, Sarunas Kalade (University of Strathclyde), Graham Schelle (AMD Adaptive and Embedded Computing Group)


1 September, 2022

Details of Workshops/Tutorial for today can be found at the individual links. All Workshops/Tutorials will be held at the Ashby Building, QUB.

Time #Room Event
09:00 – 13:00 2.015 6th Workshop on Reconfigurable Computing for Machine Learning – RCML’2022
09:00 – 13:00 1.002 Introduction to oneAPI with Intel® FPGAs
09:00 – 13:00 1.005 RFSoC-PYNQ workshop – introduction to the new PYNQ enabled RFSoC 4x2 academic platform
10:15 – 10:45   Coffee Break
13:00 – 14:00   Lunch Break
14:00 – 17:00 3.016 3rd Workshop on DevOps Support for Cloud FPGA platforms (DevOps)
14:00 – 17:00 2.014 Post CMOS reconfigurable fabrics
14:00 – 17:30 2.022 AMD HACC Workshop – Introduction to the Heterogeneous Accelerated Compute Clusters
15:15 – 15:30   Coffee Break

2 September, 2022

Details of Workshops/Tutorial for today can be found at the individual links. All Workshops/Tutorials will be held at the Ashby Building, QUB.

Time #Room Event
09:00 – 13:00 2.022 The HERMES design flow: an FPGA synthesis flow targeting space applications
09:00 – 13:00 4.005 Neural Network Accelerator Co-Design with FINN
10:15 – 10:45   Coffee Break
13:00 – 14:00   Lunch Break
14:00 – 17:00 2.021 Efficient Cryptography on Reconfigurable Hardware
15:15 – 15:30   Coffee Break